(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a structure and a simplified method for the creation of a MIM capacitor.
(2) Description of the Prior Art
The manufacturing of semiconductor devices applies a number of interacting disciplines that collectively create high performance semiconductor devices. The majority of these semiconductor devices have as function the processing of digital information, which is characterized by zero and one conditions, typically created by on-off conditions of switching transistors. In addition, hybrid functions can be provided that address not only the processing of digital signals but also address the processing of analog signals, either as a function provided by an analog semiconductor device or in collaboration with digital devices.
Device performance improvements have been sought and established by continuously decreasing device dimensions, thereby concurrently increasing device packaging density. This poses problems for a number of the typical analog components such as capacitors and inductors, which have physical dimensions that do not lend themselves to ready integration into a highly miniaturized, sub-micron device environment.
Continued reduction in device dimensions has placed increased emphasis on using copper as an interconnect material. The limitation that this approach experiences however is that the technology of creating capacitive components in a copper interconnect environment as yet presents a challenge, especially where this interconnect environment makes use of the copper damascene process.
Low resistivity metals such as aluminum and copper and their binary and ternary alloys have been widely explored as interconnects in semiconductor manufacturing. Typical examples of interconnect metals include AlxCuy, ternary alloys and other similar low resistivity metal-based alloys. Emphasis on scaling down line width dimensions in very large scale integrated (VLSI) circuitry manufacturing has led to reliability problems including inadequate isolation, electromigration and planarization. Damascene processes use metal filling of vias and lines followed by chemical mechanical polishing (CMP) of Al, Cu and Cu-based alloys, which are key elements of future wiring technologies for very large-scale system integration (VLSI) and ultra-large scale integration (ULSI).
The creation of a capacitor typically requires a complex and time-consuming sequence of processing steps, resulting in a relatively expensive component. The invention addresses this aspect of the creation of a capacitor and provides a simple, low cost process.
U.S. Pat. No. 6,384,442 B1 (Chen) shows a MIM Capacitor process.
U.S. Pat. No. 6,329,234 B1 (Ma et al.) reveals a copper compatible MIM capacitor method.
U.S. Pat. No. 5,898,200 (Sugiyama et al.) shows a capacitor and passivation layer arrangement.
U.S. Pat. No. 5,789,303 (Leung et al.) shows cap over a passivation layer.